Verification by Error Modeling J. Koerting Veranstaltung: Bau- & Planungsmanagement

Veranstaltung: Bau- & Planungsmanagement

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Verification by Error Modeling J. Koerting Veranstaltung: Bau- & Planungsmanagement1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be imminently doable by Intel fellow J. Crawford at Microprocessor Forum in October